Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years

About the role

Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc).

What you'll do

• Drives collaboration cross-functionally to achieve high-volume production with uncompromised quality
• Collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation and during ASIC bring up
• Defining and Building UVM/System Verilog testbenches from scratch or enhancing existing testbenches with focus on reuse
• Defining new DV methodologies or enhancing the existing methodologies
• End-to-end verification of one or more design blocks simultaneously while helping full chip team with integration and support

What you need

• 15–27 yrs of experience
• UVM
• Verilog
• VLSI
• Hardware
• C++
• C
• B.Sc or Company Secretary

Good to have

• Test cases