Leadership Role - DFT

About the role

This role requires close collaboration with RTL, DFT RTL, DFT Verification, Physical Design, Product Engineering Operations (PEO), ATE, and Silicon Validation teams to ensure high-quality test content, optimal coverage, tester readiness, and successful silicon deployment.

What you'll do

• Lead end-to-end ATPG strategy, implementation, and pattern validation for complex, multi-million gate SoCs powering next-generation SOCs
• Be responsible for driving all ATPG execution activities from DFT architecture definition through pre-silicon verification, production test enablement, silicon bring-up
• Define and drive ATPG methodologies, test strategies, coverage closure plans, and pattern signoff criteria
• Generate and validate scan, transition fault, cell-aware, bridge, chain diagnosis, and compression-based ATPG patterns
• Drive pattern quality improvements, tester efficiency optimization, and test cost reduction initiatives

What you need

• 16–29 yrs of experience
• VLSI
• Python
• Root cause analysis
• Perl
• Go-to-market
• Any graduate