Manager / Senior Manager – Design Verification

About the role

We are seeking an experienced Manager / Senior Manager – Design Verification to join our Silicon Engineering team in Hyderabad. In this role, you will lead and develop a high-performing verification team responsible for IP and SoC verification across multiple projects. You will drive verification planning, execution, closure, and on-time delivery while providing strong technical and people leadership.

What you'll do

• Lead and develop a high-performing Design Verification team responsible for IP and SoC verification across multiple projects
• Drive verification planning, execution, functional coverage closure, regression management, sign-off, and on-time delivery with high quality
• Provide technical leadership in SystemVerilog, UVM, assertions, constrained-random verification, coverage-driven verification, and debug methodologies
• Manage project priorities, technical risks, resource allocation, and dependencies across multiple programs
• Collaborate with Design, Architecture, Firmware, Validation, and Program Management teams across global sites

What you need

• 10–15 yrs of experience
• UVM
• Verilog
• VLSI
• Performance management
• B.Tech or B.E. or M.Tech

Good to have

• FPGA
• Python
• Prototyping
• Perl