Mixed- Signal Systems and Verification Engineer

About the role

Mixed- Signal Systems and Verification Engineer at Cadence. Become part of a hands-on development team that fosters engineering excellence, creativity, and innovation.

What you'll do

• Become part of a hands-on development team that fosters engineering excellence, creativity, and innovation
• As an AMS Verification Engineer, you will be responsible for Developing accurate and simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog
• Verifying that the behavior models are accurate representations of analog schematics
• Integrating the models with RTL
• Verifying analog functionalities against design specifications using analog behavioral models: for example, coding test benches, test scenarios, and assertions

What you need

• Verilog
• Python
• Perl
• Test cases
• Any graduate

Good to have

• FPGA
• Prototyping