NoC Design Lead

About the role

We are hiring two NoC Design Leads to own the stacked Network-on-Chip that forms the data backbone of xPU — 4 physical planes delivering 12 TB/s cross-section bandwidth. You will architect and implement coherency, routing, QoS, and bandwidth allocation across the BFOS arrays, banked SRAM, HBM controllers, UCIe links, and the host interface.

What you'll do

• Architect and implement the 4-plane stacked NoC delivering 12 TB/s cross-section bandwidth across all on-chip and off-chip endpoints
• Define topology, routing algorithms, virtual channels, and arbitration to guarantee deadlock-free, high-throughput data movement
• Design QoS and bandwidth-allocation mechanisms balancing traffic between dual BFOS arrays, 512 SRAM banks, HBM controllers, UCIe, and host
• Own the on-chip coherency protocol and its interaction with SRAM, HBM, and the host-interface coherency layer
• Drive micro-architecture, RTL, and integration of routers, network interfaces, buffers, and clock-domain crossings

What you need

• 10–18 yrs of experience
• Verilog
• Arbitration
• Python
• Perl
• M.Tech or M.Sc or B.Tech or B.E.