NOC DV Engineer

About the role

Seeking a highly skilled and self-driven Design Verification Engineer to lead verification of complex AI, Networking, Datacenter, HPC, and Interconnect IPs/Sub-systems. Expert in SystemVerilog (SV) and UVM, with hands-on experience in building reusable verification environments, UVCs/agents, sequences, scoreboards, checkers, assertions, and coverage infrastructure.

What you need

• 3–6 years in it support & networking
• Hardware
• UVM
• VLSI
• Networking
• Root cause analysis
• CI/CD
• B.Sc or B.Tech or B.E. or BCA or M.Sc or M.Tech or MCA

Good to have

• Machine learning
• Prototyping
• Verilog
• Python
• Perl