NPU Design implementation (Synthesis) Principal/Manager

About the role

The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.

What you'll do

• Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus)
• Develop and maintain synthesis scripts and flows for hierarchical and flat designs
• Drive pre-layout and post-layout timing closure across multiple voltage and process corners
• Collaborate with STA teams to resolve setup/hold violations
• Power & Area Optimization

What you need

• 4–7 yrs of experience
• VLSI
• Python
• Perl
• Verilog
• B.Sc or B.Tech or B.E. or BCA or M.Sc or M.Tech or MCA