PD Power Lead

About the role

MTS Silicon Design Engineer – PTPX Power Engineer Role Summary Responsible for power analysis, power optimization, and signoff of complex SoC/IP designs using PrimeTime PX (PTPX) and related power methodologies. The engineer will drive dynamic and leakage power convergence, identify power bottlenecks, develop power reduction strategies, and collaborate across PD, RTL, Architecture, Timing, DFT, and Power teams to achieve product power targets.

What you'll do

• Perform block, tile, and full-chip power analysis using PrimeTime PX (PTPX)
• Analyze dynamic, leakage, clock, memory, and switching power components to identify optimization opportunities
• Drive power convergence across project milestones and signoff stages
• Debug high-power hotspots and recommend architecture, RTL, clocking, and physical design optimizations
• Execute power regression flows and generate power dashboards, reports, and trend analysis

What you need

• 7–10 yrs of experience
• VLSI
• Python
• Shell scripting
• Perl
• B.Tech or B.E. or M.Tech

Good to have

• Machine learning