PE Logic Design

About the role

Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our PCIe IP design team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. This full-time position will allow the candidate to contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe standards.

What you'll do

• Contribute to the architecture and micro-architecture of next generation PCIe IP
• Implement these designs in System Verilog
• Collaborate with the verification team to verify the IPs
• Participate in prototyping of the IPs in cutting edge FPGAs
• Contribute to support of existing generations of the IPs

What you need

• 8–14 yrs of experience
• Verilog
• Prototyping
• PhD or B.Tech or B.E.