Physical Design Engineer (Staff / Sr. Staff / Principal)

About the role

As a Staff/Sr. Staff/Principal Physical Design Engineer at Velaura AI, you will be responsible for driving the physical implementation and sign-off of critical blocks for next-generation AI and high-performance computing silicon. You will own complex designs from RTL to GDSII, including synthesis, floorplanning, place and route, clock tree synthesis, timing closure, extraction, physical verification, EM/IR, and final sign-off.

What you'll do

• Own critical design blocks and drive them from RTL to GDSII through synthesis, floorplanning, place and route, timing closure, and sign-off
• Implement and optimize floorplans, power plans, placement, clock tree synthesis, routing, extraction, and sign-off closure for high-performance designs
• Drive timing convergence across multiple modes and corners while meeting aggressive frequency, power, area, and schedule goals
• Work closely with RTL and architecture teams to understand micro-architecture and evaluate feasibility, timing, power, congestion, and area tradeoffs
• Develop and improve physical design methodologies, implementation recipes, and automation flows to optimize PPA and improve design productivity

What you need

• 8–14 yrs of experience
• VLSI
• Python
• Perl
• B.Tech or B.E.