Physical Design Engineer- Static Timing Analysis (STA)

About the role

We are looking for a highly skilled Physical Design Engineer with deep expertise in static timing analysis using Cadence Tempus. The ideal candidate will own timing closure across multiple blocks and top-level designs, working closely with synthesis, PD, and signoff teams to achieve high-performance, low-power SoC designs.

What you'll do

• Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration
• Work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation

What you need

• VLSI
• Any graduate

Good to have

• Python
• Linux