Physical Design Engineer

About the role

We are seeking an experienced Physical Design Engineer with 6–15 years of industry experience to join our VLSI/ASIC engineering team. The ideal candidate will have strong hands-on expertise across the physical implementation flow, with particular emphasis on Cadence Innovus and Static Timing Analysis (STA) .

What you'll do

• Perform end-to-end physical design activities including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization
• Develop and implement physical design strategies for complex digital blocks and full-chip designs
• Use Cadence Innovus extensively for placement, CTS, routing, timing optimization, and design closure
• Analyze timing reports and perform STA to identify setup and hold violations and drive timing closure
• Work on congestion analysis, placement optimization, buffering, cell sizing, and other techniques to improve PPA and timing

What you need

• 6–15 yrs of experience
• VLSI
• B.Tech or B.E.

Good to have

• Python

What you get

• ₹30 L–₹75 L a year