Physical Design Lead(High Speed IP's)

About the role

In this role, you will drive the physical implementation of industry-leading high-speed interface IPs including DDR, LPDDR, GDDR, PCIe, and other next-generation mixed-signal PHY solutions used across client, server, and graphics products.

What you'll do

• Drive the physical implementation of industry-leading high-speed interface IPs including DDR, LPDDR, GDDR, PCIe
• Work closely with architects, circuit designers, RTL, package, power integrity, signal integrity, SoC
• Own end-to-end implementation activities Drive high-frequency timing closure for challenging datapaths and clock distribution networks
• Partner with architects and circuit designers to optimize PHY architectures for performance, power, and implementation efficiency
• Develop and deploy innovative implementation methodologies to improve design quality, productivity, and scalability

What you need

• 12–22 yrs of experience
• VLSI
• B.Tech or B.E. or M.Tech