Physical Verification Engineer (Staff / Sr. Staff)

About the role

As a Staff/Sr. Staff Physical Verification Engineer at Velaura AI, you will own block-level and full-chip physical verification and signoff for next-generation AI and high-performance computing silicon. You will drive physical verification from block-level implementation through full-chip integration and final tape-out, working on complex SoC designs targeting advanced process technologies.

What you'll do

• Own block-level and full-chip physical verification signoff, including DRC, LVS, ERC, PERC, antenna, ESD/EOS, and related reliability checks for complex ASIC/SoC designs
• Drive tape-out readiness and signoff closure through violation triage, root-cause analysis, waiver management, schedule tracking
• Execute and debug physical verification using industry-standard tools such as Siemens Calibre and Synopsys IC Validator (ICV), including complex connectivity
• Correlate Calibre/ICV results with Cadence Innovus and/or Synopsys Fusion Compiler implementation databases and drive physical fixes through iterative verification to…
• Perform hands-on physical implementation and ECO changes, including routing and via edits, metal-shape modifications, cell movement, filler/decap/endcap updates

What you need

• 8–14 yrs of experience
• Inventory counting
• VLSI
• Python
• Root cause analysis
• Perl
• Linux
• B.Tech or B.E.