Power-Domain Verification Lead

About the role

Verification Lead Power Aware Simulation position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT. You should have prior knowledge and experience in power aware simulations with UPF verification and UVM testbench development.

What you'll do

• Execute power-aware simulations and debug failures related to power intent
• Integrate UPF with UVM testbenches and VIPs
• Expertise in verifying design at RTL (SOC) level and gate-level simulation
• Create directed and constrained-random tests for low-power scenarios
• Reset behavior across power domains

What you need

• 10–18 yrs of experience
• UVM
• Verilog
• Python
• Perl
• B.Tech or B.E. or M.Tech