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Engineering, Principal Engineer - 17322

Synopsys (incl. Ansys)·Bengaluru

Pay not stated10–18 yrsFull-time
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About the role

Principal ASIC Digital Design Engineer (Verification) Principal ASIC Digital Design Engineer (Verification)

What you'll do

  • Build scalable verification infrastructure from the ground up, designing environments that support complex IP and SoC projects across global teams
  • Lead and mentor verification engineers, providing technical guidance on UVM, SystemVerilog, flow optimization, and debugging strategies
  • Drive technical initiatives independently, managing high-impact assignments from concept through deployment and adoption
  • Collaborate with EDA tool development teams to influence product roadmaps, provide feedback, and optimize verification workflows for real-world use cases
  • Troubleshoot and refine verification processes for internal teams and customers, diagnosing flow bottlenecks and delivering solutions that stick

What you need

  • 10–18 yrs of experience
  • UVM
  • Verilog
  • Python
  • B.Tech or B.E.

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