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Principal ASIC Verification Engineer - DDR/LPDDR

Synopsys (incl. Ansys)·Bengaluru

Pay not stated8–14 yrsFull-time
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About the role

Principal ASIC Verification Engineer - DDR/LPDDR at Synopsys (incl. Ansys). Lead a team of verification engineers through full IP verification cycles, from test plan definition through coverage closure and signoff.

What you'll do

  • Lead a team of verification engineers through full IP verification cycles, from test plan definition through coverage closure and signoff
  • Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations
  • Define test plans that cover corner cases, protocol compliance, and system-level interactions, then review and guide implementation across the team
  • Write and debug complex testbenches, checkers, and assertions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable
  • Extract, analyze, and drive functional coverage and code coverage metrics to closure, identifying gaps and adjusting strategy in real time

What you need

  • 8–14 yrs of experience
  • Verilog
  • UVM
  • Test cases
  • M.Tech or B.Tech or B.E.

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