Principal Cache RTL Design - CPU Team

About the role

Design optimization for implementing power efficient IP, implementing the RTL using low power techniques Responsible for the inter IP integration issues resolution Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem.

What you'll do

• Responsible for the inter IP integration issues resolution Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem
• Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Architecting

What you need

• 15–27 yrs of experience
• Verilog
• VLSI
• B.Tech or B.E.

Good to have

• Python
• Perl