Principal CAD Engineer Digital Verification

About the role

We are seeking a CAD Engineer specializing in Digital Verification to build, enhance, and support scalable verification infrastructure, methodologies, and EDA automation flows for ASIC/SoC development. The role focuses on enabling verification teams with robust regression systems, automation frameworks, and advanced methodologies (UVM, coverage, Continuous Integration flows) to improve productivity, debug efficiency, and time-to-tapeout.

What you'll do

• Act as the primary support interface for Design & Verification (DV) teams to troubleshoot issues in simulation, regression, coverage, and debug flows
• Collaborate with DV teams to identify bottlenecks and provide practical solutions or workarounds
• Support adoption of modern verification techniques (coverage-driven, formal, emulation) through guidance and issue resolution
• Deploy, integrate, and maintain CAD tools, scripts, and environments supporting digital verification flows
• Provide day-to-day support for EDA tools (VCS, Xcelium, Verdi, vManager, etc.) and resolve tool/flow-related issues

What you need

• 12–22 yrs of experience
• Verilog
• UVM
• CI/CD
• Python
• Perl
• Linux
• B.Tech or B.E.

Good to have

• MATLAB
• Machine learning
• LLMs