Principal Design Engineer

About the role

B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field 7–10 years of hands-on DV experience in semiconductor/ASIC/SoC companies Deep expertise in SystemVerilog and UVM (Universal Verification Methodology) Proficiency in coverage-driven verification — functional, code, and toggle coverage

What you'll do

• Execution and Technical Leadership
• Cross-functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams

What you need

• 7–10 yrs of experience
• UVM
• Verilog
• Test cases
• Root cause analysis
• VLSI
• B.Tech or B.E. or M.Tech