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Principal Design Engineer

Cadence·Bengaluru

Pay not stated7–13 yrsFull-time

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About the role

This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently and collaboratively to complete tasks within required project timelines with high quality.

What you'll do

  • Drive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process
  • Work with verification team to specify coverage points, testing strategy, corner conditions and stimulus creation

What you need

  • 7–13 yrs of experience
  • Test cases
  • Circuit design
  • Any graduate

Good to have

  • C++
  • Verilog
  • Python
  • C
  • Git

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