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Principal Design Engineer

Cadence·Bengaluru

Pay not stated8–14 yrsFull-time
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About the role

Principal Design Engineer at Cadence. Design Verification for interconnect IP.

What you'll do

  • Design Verification for interconnect IP
  • Crafting verification plans and executing on those plans to verify highly complex and configurable designs
  • Responsible for coverage collection and closure
  • Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
  • BS (or higher) in EE/Computer Engineering

What you need

  • 8–14 yrs of experience
  • UVM
  • Verilog
  • Perl
  • Linux
  • B.Tech or B.E.

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