Principal Design Engineer

About the role

The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.

What you'll do

• Identifying and implementing RTL changes for DFT
• Performing scan insertion, LEC checks, low power CLP checks
• Developing timing constraints for test mode timing closure
• Scan and ATPG for different fault models
• Boundary scan, ACJTAG, IEEE 1500 implementation and verification

What you need

• 7–12 yrs of experience
• VLSI
• Accounts receivable
• System design
• Customer success
• Learning and development
• B.Tech or B.E. or M.Tech or Diploma

Good to have

• Python
• Perl