Principal Design Verification Engineer

About the role

We are seeking talented Design Verification Professionals with proven expertise in industry-standard protocols such as PCIe and CXL. You will play a key role in the functional verification of designs, from developing block-level and system-level verification plans to writing test sequences, executing tests, and collecting and closing coverage.

What you'll do

• Develop and execute block-level and system-level verification plans
• Write and execute test sequences and collect and close coverage
• Collaborate with RTL designers to debug failures and refine verification processes
• Utilize coding and protocol expertise to contribute to functional verification
• Develop user-controlled random constraints in transaction-based verification methodologies

What you need

• 12–22 yrs of experience
• UVM
• Test cases
• Any graduate