Principal Engineer – ASIC SoC Design

About the role

Seeking a Principal Engineer – ASIC SoC Design to drive IP, Subsystem, and SoC development for next‑generation memory and storage products, requiring strong hands‑on expertise in micro‑architecture, RTL design, and end‑to‑end SoC execution, along with close collaboration across global teams.

What you'll do

• Own end‑to‑end IP and SOC development from micro‑architecture through RTL compose, integration, and physical hardware assistance
• Own IP and Subsystem design from scratch, ensuring high‑quality, reusable RTL
• Drive SoC integration, including CDC, lint, synthesis, STA, and power analysis
• Define and review module interfaces and system‑level architecture
• Collaborate closely with Architecture, Verification, FW, DFT, Synthesis, and Physical Design teams

What you need

• 12–22 yrs of experience
• Verilog
• VLSI
• Any graduate