Principal Engineer Design

About the role

We are seeking a highly motivated Principal Engineer Design to lead the physical implementation and timing closure of advanced low-power SoCs targeting the IoT and MCU markets. This role offers the opportunity to drive end-to-end physical design execution, optimize power, performance, and area (PPA), and influence methodology improvements that enable successful silicon delivery.

What you'll do

• Lead physical design and timing closure for complex low-power SoCs targeting IoT and MCU applications
• Manage end-to-end physical implementation from floor planning to final signoff while meeting Power, Performance, and Area (PPA) objectives
• Drive and optimize die area, timing, power, and performance for both hierarchical block-level and full-chip designs
• Own critical physical design activities, including package co-design, floor planning, power planning, power grid design, place-and-route (P&R)
• Ensure successful timing convergence across multiple operating modes and process, voltage, and temperature (PVT) corners

What you need

• 12–22 yrs of experience
• VLSI
• IoT
• Verilog
• Customer success
• B.Tech or B.E.