Principal Engineer-Design (SoC Integration and RTL/IP)

About the role

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization?

What you'll do

• Perform top-level and subsystem integration of processors, memories, peripherals, and custom IPs
• Integrate IPs using proprietary bus interfaces and AMBA AXI, AHB / APB protocols
• Handle clock/reset integration, interrupt routing, address mapping, and pad / pin connectivity
• Resolve chip-level Lint / Synthesis / Timing issues perform CDC / RDC analysis and implement relevant fixesOwnership of post-silicon debug and ECO revisions of the chip
• Develop synthesizable RTL using SystemVerilog

What you need

• Verilog
• Any graduate