Principal Engineer Design-Synthesis, LEC & CLP

About the role

We are looking for an experienced RTL2GDS Frontend expert with 10+ years of hands-on experience in Synthesis, LEC, and Low Power Verification (CLP) for complex SoC designs. Your role Key responsibilities in your new role Develop, enhance, and maintain front-end design flows and automation frameworks to improve productivity and design quality

What you'll do

• Develop, enhance, and maintain front-end design flows and automation frameworks to improve productivity and design quality
• Drive synthesis convergence and support design optimization across advanced technology nodes
• Perform design bring-up, debug, and issue resolution throughout the implementation cycle
• Execute and close Logic Equivalence Check (LEC) and low-power verification activities
• Collaborate closely with RTL, STA, DFT, and Physical Design (PD) teams to ensure seamless design integration and execution

What you need

• 10–18 yrs of experience
• VLSI
• Python
• Travel booking
• Customer success
• Perl
• B.Tech or B.E.