Principal Engineer, Design Verification Engineering

About the role

The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI.

What you'll do

• Lead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff
• Verify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies
• Define and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance
• Collaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies
• Drive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early

What you need

• 12–22 yrs of experience
• UVM
• Verilog
• C++
• C
• Python
• Machine learning
• B.Tech or B.E. or M.Tech

Good to have

• FPGA
• Test cases