Principal Engineer , DFT

About the role

Principal Engineer , DFT at Renesas JP. Define and drive SoC-level DFT architecture and test strategy, including Scan, ATPG, MBIST, LBIST, JTAG/IJTAG, SSN, and test compression.

What you'll do

• Define and drive SoC-level DFT architecture and test strategy, including Scan, ATPG, MBIST, LBIST, JTAG/IJTAG, SSN, and test compression
• Own the complete DFT flow from test architecture, RTL design & integration, DFT verification, scan insertion, ATPG, coverage closure, and signoff
• Drive silicon bring-up, silicon debug, diagnosis, yield improvement, and production test enablement
• Develop and deploy scalable DFT methodologies, automation frameworks, and best practices
• Collaborate with Design, Verification, Physical Design, and Test Engineering teams

What you need

• 15–27 yrs of experience
• VLSI
• Verilog
• Any graduate