Principal Engineer, HBM Design Verification

About the role

This role is perfect for a hands-on silicon verification expert who is passionate about developing best-in-class verification methodologies, testbench design, AI enabled verification and developing novel solutions to improve quality and efficiency of verification workflows.

What you'll do

• Define and drive verification architecture and methodology for next generation HBM designs
• Develop verification plans, coverage strategies, and sign-off criteria
• Architect and implement UVM-based testbenches and reusable verification components
• Apply Formal Verification techniques for critical
• Collaborate strictly with build teams to ensure verification completeness and quality

What you need

• 12–22 yrs of experience
• UVM
• Verilog
• PhD or B.Tech or B.E.

Good to have

• Python