Principal Engineer

About the role

We are looking for an experienced SoC/IP Verification Engineer to lead and drive the verification of complex semiconductor designs. The role involves defining verification strategies, architecting and developing scalable constraint-random verification environments, and driving verification closure at both subsystem and SoC levels.

What you'll do

• Lead and contribute to the definition of verification architecture and strategy for IPs, subsystems, and SoCs
• Develop robust constraint-random verification environments from scratch using SystemVerilog and UVM methodologies
• Build reusable verification components, assertions, coverage models, and testbenches to ensure comprehensive design validation
• Perform RTL verification, power-aware simulations, Gate-Level Simulations (GLS), boot verification, and drive end-to-end verification closure
• Develop C-based tests, debug complex functional issues using Tarmac, and collaborate closely with design and software teams

What you need

• UVM
• Verilog
• C
• Customer success
• Any graduate