Principal Engineer - IP Verification

About the role

Seeking highly motivated, energetic, team-oriented Individual contributor willing to take the challenge of delivering the first pass success of complex IPs using the latest advanced verification languages and methodology.

What you'll do

• Evaluate and deploy the evolving verification methodologies to handle increasingly complex IP/SubSystem designs within aggressive, market-driven schedules
• Own and ensure quality adherence during all stages of the project cycle
• Building and Influencing technological innovations for self and in team environment

What you need

• 10–15 yrs of experience
• Verilog
• Embedded C
• UVM
• C++
• Any graduate