Principal Engineer SoC Design Verification

About the role

The Principal SoC Verification Lead provides technical leadership for verification of complex Smart Analog & Sensor SoCs. The role is responsible for verification strategy, methodology, planning, execution, and signoff across subsystem and full-chip environments. This individual will drive verification quality across processor, accelerator, memory, connectivity, and sensor subsystems while ensuring comprehensive coverage and first-silicon success.

What you'll do

• Development of chip-level and subsystem-level verification strategies
• Definition of test plans, coverage plans and verification methodologies including UVM
• Leadership of verification engineers across internal and external resources
• Lead verification of interfaces, bus interconnects, DMA engines, memory architectures, security and safety functions, data processing pipelines
• Coordinate subsystem and SoC-level verification activities

What you need

• 15–27 yrs of experience
• UVM
• VLSI
• Test cases
• Any graduate

Good to have

• Prototyping