Principal Engineer, SRAM Design

About the role

The role requires strong hands-on knowledge of SRAM and bitcells, sense amplifiers, address decoders, control logic, etc. The successful candidate will work closely with layout, CAD, process integration, testchip, and other partner teams to deliver robust, production-ready memory solutions.

What you'll do

• Design, Develop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders
• Evaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions
• Own transistor-level simulation and signoff using Spectre/FineSim, or comparable tools, including PVT corners, Monte Carlo analysis
• Partner with layout engineers on floorplanning, bitcell-array composition, matching, critical-net routing, clock and control distribution, parasitic reduction
• Develop or improve automation for simulation setup, corner execution, results extraction, validation, and regression using Python, Tcl, Perl, SKILL, or similar languages

What you need

• Circuit design
• VLSI
• Python
• Perl
• Calibration
• B.Sc or M.Sc or PhD or B.Tech or B.E.

Good to have

• Travel booking
• LLMs