Principal Formal Verification Engineer

About the role

We are looking for a Principal Formal Verification Engineer with 10+ years of experience to lead formal verification efforts for complex semiconductor and silicon designs. This role will be responsible for driving verification strategy, improving design quality, and mentoring engineers while working closely with design, architecture, and validation teams.

What you'll do

• Lead formal verification activities for block-level and subsystem-level designs
• Define formal verification plans, methodologies, and closure criteria for complex digital designs
• Develop and execute formal verification environments, assertions, properties, and checkers
• Collaborate with RTL designers, architects, and verification teams to understand design intent and verification requirements
• Identify functional corner cases, protocol issues, and design bugs early in the development cycle

What you need

• 10–18 yrs of experience
• Verilog
• Root cause analysis
• B.Tech or B.E.

Good to have

• Python
• Perl