Principal IP verification engineer

About the role

In this role you will be responsible for verifying complex IPs involving memory controllers, and interconnects, collaborating with global design and architecture teams.

What you'll do

• Develop and execute verification plans for memory controllers, interconnects and other infrastructural IPs
• Build scalable SystemVerilog/UVM-based verification environments with reusable UVM components (agents, monitors, scoreboards)
• Own end-to-end IP verification sign-off
• Achieve high-quality metrics including functional coverage and code coverage
• Manage regressions and debug failures

What you need

• 10–18 yrs of experience
• UVM
• Verilog
• Any graduate