Principal Logic Design Engineer - UALink IP/Subsystem

About the role

We are looking for a Principal Logic Design Engineer with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for UALink-based IP/subsystems .

What you'll do

• Lead architecture and RTL development for UALink IP/subsystems
• Translate protocol and system requirements into scalable hardware architecture
• Design high-bandwidth, low-latency data paths and control logic
• Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability
• Define interfaces between UALink and other SoC/interconnect components

What you need

• 10–15 yrs of experience
• Verilog
• VLSI
• Arbitration
• Any graduate