Principal Physical Design Methodology and Execution

About the role

We are seeking a highly experienced lead timing closure and physical design closure efforts across complex, advanced-node SoC programs. The ideal candidate brings approximately 20 years of hands-on and leadership experience in the semiconductor industry, with a strong track record of driving multiple designs through STA closure and tapeout.

What you'll do

• Own and drive end-to-end STA (Static Timing Analysis) and Physical Design (PD) closure for complex SoC/ASIC designs at advanced technology nodes
• Lead timing closure strategy across multiple blocks/chips, including setup/hold analysis, clock domain crossing, multi-corner multi-mode (MCMM) sign-off, and margining
• Drive full-chip tapeout readiness, ensuring timing, physical, and sign-off criteria are met within schedule
• Partner closely with RTL, synthesis, place-and-route, and physical verification teams to resolve timing and physical closure bottlenecks
• Define and continuously improve STA and PD closure methodologies, flows, and best practices across projects

What you need

• 20–30 yrs of experience
• VLSI
• Root cause analysis
• B.Tech or B.E.