Principal Physical Verification Engineer

About the role

We are seeking a talented Physical Verification Design Engineer to join our VLSI design team. This role involves ownership of full-chip and block-level physical verification (PV) signoff, ensuring designs meet foundry and reliability requirements. The candidate will collaborate closely with physical design, PDK, CAD, and tapeout teams to deliver high-quality silicon.

What you'll do

• Perform physical verification (PV) for block-level and full-chip designs, including: Design Rule Check ( DRC )
• Layout Versus Schematic ( LVS )
• Electrical Rule Check ( ERC )
• Antenna, density, and reliability checks
• Drive signoff closure by identifying and resolving PV violations efficiently

What you need

• Inventory counting
• VLSI
• Any graduate