ASIC Digital Design, Principal Engineer - 16923

About the role

Principal RTL Design Engineer, Interconnect IP (PCIe digital design and architecture) Principal RTL Design Engineer, Interconnect IP (PCIe digital design and architecture)

What you'll do

• Own the PCIe digital architecture and drive RTL design execution across block, subsystem, and IP integration levels
• Define micro-architecture, design specifications, and implementation strategies for high-performance, power-efficient, and scalable PCIe IP
• Lead end-to-end digital design activities from architecture definition through RTL development, debug, design convergence, and post-silicon support
• Serve as the technical authority for PCIe design, resolving complex issues and making critical design trade-offs that affect current and next-generation IP
• Mentor ASIC digital design engineers through design reviews, technical feedback, and hands-on problem solving

What you need

• 12–22 yrs of experience
• VLSI
• Verilog
• B.Tech or B.E.

Good to have

• Python
• Perl