Principal SOC Physical Verification & Integration Specialist

About the role

We are seeking a thorough SOC Physical Verification & Integration Specialist to drive the physical assembly and signoff of our next-generation SOCs. In this role, you will own the physical integration strategy from the floorplan stage through to tapeout, ensuring seamless assembly of massive multi-hierarchical blocks.

What you'll do

• Top-Level Physical Integration: Drive the full-chip physical assembly of very large-scale SOCs (e.g., multi-billion transistor designs)
• Manage top-level floorplanning, bump planning, global power grid (PG) integration, and top-level clock/routing integration
• Hierarchical Verification Methodology: Architect and deploy highly efficient, hierarchical physical verification (PV) flows
• Define the boundary conditions, abstraction models, and interface rules required to assemble heavily partitioned, massive-scale designs
• Cross-Functional Collaboration: Partner tightly with the Physical Design (PD) and Static Timing Analysis (STA) teams

What you need

• 14–25 yrs of experience
• Inventory counting
• Python
• VLSI
• Perl
• B.Tech or B.E.