Principal SoC Signoff Engineer

About the role

The Principal Engineer, SoC Signoff has a deep understanding about how timing constraints are to be written across functional and test modes. They not only leads but mentors engineers towards designing and delivering full chip, complex Ips, and critical interface multi-mode timing constraints.

What you'll do

• Lead and own all phases of timing-constraint development for complex SoCs and digital, AMS, and SerDes IPs
• Define signoff margins for ASIC implementation and static timing analysis (STA), from specification through production
• Establish processes for multi-voltage and dynamic voltage and frequency scaling (MV/DVFS) STA signoff, and develop shift-left methodologies for STA
• Provide technical mentorship to a high-performing engineering team, including recent graduates
• Champion the development, deployment, and maintenance of AI/ML-enabled STA methodologies in collaboration with leading EDA partners

What you need

• 12–22 yrs of experience
• Verilog
• VLSI
• Machine learning
• B.Tech or B.E.