Principal Synthesis, STA Engineer

About the role

As a P5 Synthesis & STA Engineer, you will provide technical leadership for Synthesis, STA, and timing closure of complex high-performance SoCs with large digital and analog interfaces. You will drive full-chip timing analysis and closure for complex, multi-GHz SoC, establish robust top-down closure methodologies, and solve complex QoR challenges spanning RTL, synthesis, constraints, clocking, and physical implementation.

What you'll do

• Lead and own Synthesis and STA closure for complex, high-performance, multi-GHz SoCs across IP, subsystem, partition, and full-chip levels
• Develop, validate, and review complex timing constraints spanning IP, subsystem, partition, and full-chip hierarchies
• Drive full-chip timing signoff across multi-mode, multi-corner scenarios and establish a robust top-down timing closure methodology, driving constraints, budgets
• Demonstrate strong expertise in AOCV/SOCV methodologies, variation-aware timing analysis, and advanced-node timing signoff
• Drive top-level clock planning and balancing across partitions and interfaces, working with Physical Design teams to optimize clock topology, implementation, and routing

What you need

• 10–15 yrs of experience
• Travel booking
• VLSI
• B.Tech or B.E. or M.Tech