Principal Verification Engineer, Digital IP

About the role

MME's Digital IP team produces design solutions covering the very wide range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low-power devices to highly integrated, high-performance, multi-cohort devices compliant with the latest automotive and industrial safety and security standards.

What you'll do

• Responsible for the pre-silicon verification of IP modules or, IP subsystems
• Responsible for defining and writing IP verification plans based on requirements documents (industry standards, product requirements
• Interface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP or subsystem
• Responsible for executing verification plan according to the product specification and verification requirements defined by product architects
• Responsible for architecting, developing, debugging and running UVM based verification environment for RTL simulation

What you need

• 10–18 yrs of experience
• UVM
• Verilog
• C++
• C
• FPGA
• Test cases
• B.Tech or B.E. or B.Sc or BCA

Good to have

• Python
• Perl