- Can I apply
- Needs PhD or B.Tech or B.E. · 7–13 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site
Read from the company's own careers page; you apply on their site.
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About the role
We are seeking an experienced DFT Engineer (7–12 years) with strong hands-on expertise in Scan Insertion, ATPG, and Gate-Level Simulation (GLS) for complex SoC designs. The candidate will be responsible for implementing and verifying scan architectures, performing scan insertion, generating and analyzing ATPG patterns for stuck-at and transition faults, and executing GLS with and without SDF for DFT validation.
What you need
- 7–12 yrs of experience
- Verilog
- VLSI
- Any graduate
Similar jobs
- Can I apply
- Needs PhD or B.Tech or B.E. · 7–13 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site
- Can I apply
- Needs PhD or B.Tech or B.E. · 7–13 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site
- Can I apply
- Needs PhD or B.Tech or B.E. · 7–13 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site