Project Lead II - VLSI

About the role

We are seeking a highly skilled Senior Physical Design Engineer . The ideal candidate will have hands-on experience in the complete ASIC Physical Design flow, from netlist to GDSII, across advanced technology nodes. The role requires expertise in floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, power optimization, and physical verification while working closely with RTL, DFT, and STA teams.

What you'll do

• Perform end-to-end Physical Design implementation for complex SoC and ASIC designs
• Develop floorplans considering power, timing, congestion, and area optimization
• Execute placement, optimization, CTS, routing, and post-route optimization
• Perform timing closure across multiple PVT corners and modes
• Resolve setup and hold timing violations

What you need

• 12–15 yrs of experience
• VLSI
• Any graduate