R&D Engineering, Staff Engineer - 17912

About the role

R&D Engineering, Staff Engineer (Design Verification/ VIP Verification Engineers) R&D Engineering, Staff Engineer (Design Verification/ VIP Verification Engineers)

What you'll do

• Design, develop, and maintain Verification IP using SystemVerilog and UVM for industry-standard protocols including AMBA, PCIe, USB, Ethernet, UEC, UAL, and MIPI
• Build comprehensive verification plans that map protocol specifications to testable scenarios, coverage goals, and corner case strategies
• Code sequences, test scenarios, and checkers that drive coverage-based verification across functional and code coverage dimensions
• Debug complex simulation failures across multi-layer protocol stacks, identifying root causes in both VIP logic and customer integration environments
• Enhance existing VIP products for performance, reusability, and scalability as protocols evolve and customer use cases expand

What you need

• 5–9 yrs of experience
• UVM
• Verilog
• Troubleshooting
• Test cases
• B.Tech or B.E. or M.Tech or B.Sc or BCA or MCA or M.Sc