RTL Design & Validation Lead with DDR protocols exp

About the role

The focus of this role is to plan, build, and execute the design and validation of new and existing features for AMD’s DDR IPs and custom IPs. To work on custom IP projects. Focus on improving accuracy, convergence speed, and adaptability of calibration routines Create and execute validation plans to verify the correctness and performance of calibration firmware, algorithms and custom IPs.

What you'll do

• Ensure seamless interaction between hardware and firmware components, delivering reliable calibration performance aligned with silicon and platform requirements
• Work on custom IP projects
• Perform system-level bring-up and debug activities to identify and resolve issues related to memory training and stability Work closely with silicon design
• Ensure seamless integration and interoperability across the full memory subsystem Stay updated with emerging DDR technologies and calibration techniques

What you need

• 12–22 yrs of experience
• Verilog
• Calibration
• B.Tech or B.E. or M.Tech or B.Sc or M.Sc

Good to have

• C
• Git