RTL Design Engineer — Silicon Team

About the role

When you apply, tell us your primary strength: Datapath — execution units, register files, floating-point arithmetic Fabric & Interconnect — on-chip networks, PCIe, high-speed serial, CDC Pipeline Control — scoreboards, dispatch logic, DMA, CSR Orchestration & Integration — SoC top-level, AXI bus fabric, system controller

What you'll do

• Fabric & Interconnect — Build a multi-stage switch fabric with credit-based flow control, high-speed serial interfaces (8b/10b, CRC, ARQ), PCIe Gen3 x16 endpoint
• Orchestration & Integration — Build the RISC-V-based system management controller, AXI4-Lite multi-master bus infrastructure
• Peripherals & Security — Integrate DDR4 memory controller, implement silicon root-of-trust/secure boot/key management, build JTAG debug controller (IEEE 1149.1)
• Performance & PPA — Run synthesis continuously from early RTL, identify and resolve critical timing paths, run power estimation from switching activity

What you need

• 5–10 yrs of experience
• Verilog
• Python
• Any graduate